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this is information on a product in full production. january 2015 docid025792 rev 2 1/34 STC3117 gas gauge ic with battery charger control for handheld applications datasheet - production data features ? patented ? optimgauge? ? algorithm ? for ? accurate ? battery ? capacity ? calculation ? robust initial open-c ircuit-voltage (ocv) measurement at power up ? programmable low battery alarm ? missing/swapped battery detection ? average current internal calculation ? end-of-charge detection ? internal temperature sensor ? battery swap detection with protection against false battery insertion ? low power: 40 a in voltage-only mode, 2 a max in standby mode ? 1.49 x 1.594 mm 9-bump csp package applications ? mobile phones, multimedia players, digital cameras ? portable medical equipment description the STC3117 includes the stmicroelectronics optimgauge? algorithm. it provides accurate battery state-of-charge (soc) monitoring, tracks battery parameter changes with operation conditions, temperature, and aging, and allows the application to get a battery state-of-health (soh) indication. an alarm output signals low soc or low voltage conditions and also indica tes fault conditions like a missing or swapped battery. csp (1.49 x 1.594 mm) www.st.com
contents STC3117 2/34 docid025792 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 absolute maximum ratings and operating c onditions . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 battery monitoring functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6.1.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1.2 battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1.3 internal temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.4 current sensing in mixed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.5 soc change rate in voltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 STC3117 gas gauge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.1 coulomb counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.2 voltage gas gauge algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.3 mixed mode gas gauge system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 power-up and battery swap detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 read and write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 register map and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.3 reg_mode and reg_ctrl register description . . . . . . . . . . . . . . . . 25 7.2.4 ocv table register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid025792 rev 2 3/34 STC3117 contents 34 8.1 flip chip csp 1.49 x 1.594 x 0.4 mm (n5) with coating ball printing package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
block diagram STC3117 4/34 docid025792 rev 2 1 block diagram figure 1. STC3117 internal block diagram ad converter control registers i 2 c interface vin gnd sda scl vcc cs 32768 hz time base 1.2 v reference ram and id registers mux oscillator cs+ cs- temperature sensor cd batd control logic & state machine alm battery detection and charge control
docid025792 rev 2 5/34 STC3117 pin assignment 34 2 pin assignment figure 2. STC3117 pin connections (top view) table 1. STC3117 pin description csp bump pin no. pin name type (1) 1. i = input, 0 = output, od = open drain, a = analog, d = digital, nc = not connected function c3 alm o/od alarm signal output, open drain, external pull-up with resistor a2 sda i/od i 2 c serial data b2 scl i_d i 2 c serial clock a3 gnd ground analog and digital ground b3 cs i_a current sensing input b1 batd i/oa battery detection input a1 cd o/od battery charge inhibit (active high output) c2 vcc supply power supply c1 vin i_a battery voltage sensing input top view (balls are underneath) gnd cd cs vin alm scl batd vcc sda csp (1.49 x 1.594 mm)
absolute maximum ratings and operating conditions STC3117 6/34 docid025792 rev 2 3 absolute maximum ratings and operating conditions table 2. absolute maximum ratings symbol parameter value unit v ccmax maximum voltage on vcc pin 6 v v io voltage on i/o pins -0.3 to 6 t stg storage temperature -55 to 150 c t j maximum junction temperature 150 esd electrostatic discharge (hbm: human body model) (1) 1. tested in compliance with mil-883-h, aec-q100-002d and jedec jesd22-a114f 2kv electrostatic discharge (mm: machine model) (2) 2. tested in compliance with mil-883-h, aec-q100-003e and jedec jesd22-a115a 150 v table 3. operating conditions symbol parameter value unit v cc operating supply voltage on v cc 2.7 to 4.5 v v min minimum voltage on v cc for ram content retention 2.0 t oper operating free air temperature range -40 to 85 c t perf -20 to 70
docid025792 rev 2 7/34 STC3117 electrical characteristics 34 4 electrical characteristics table 4. electrical characteristics (2.7 v < v cc < 4.5 v, -20 c to 70 c) symbol parameter conditions min typ max units supply i cc operating current consumption average value over 4 s in voltage mode 40 a average value over 4 s in mixed mode 80 i stby current consumption in standby standby mode, inputs = 0 v batd_pu bit = 0 2 i pdn current consumption in power-down v cc < uvlo th , inputs = 0 v 1 uvlo th undervoltage threshold (v cc decreasing) 2.5 2.6 2.7 v uvlo hyst undervoltage threshold hysteresis 100 mv por power-on reset threshold (v cc decreasing) 2.0 v current sensing vin_gg input voltage range -40 +40 mv i in input current 500 na adc_res ad converter granularity 5.88 v adc_offset ad converter offset cs = 0 v -3 3 lsb adc_time ad conversion time 500 ms adc_acc ad converter gain accuracy at full scale (using external sense resistor) 25 c0.5 % over temperature range 1 f osc internal time base frequency 32768 hz osc_acc internal time base accuracy 25 c, v cc = 3.6 v 2 % over temperature and voltage ranges 2.5 cur_res current register lsb value 5.88 v battery voltage and temperature measurement vin_adc input voltage range v cc = 4.5 v 0 4.5 v lsb lsb value voltage measurement 2.20 mv temperature measurement 1 c adc_time ad conversion time 250 ms volt_acc battery voltage measurement accuracy 2.7 v < vin < 4.5 v, v cc = vin, 25 c -0.25 +0.25 % over temperature range -0.5 +0.5 temp_acc internal temperature sensor accuracy -3 3 c
electrical characteristics STC3117 8/34 docid025792 rev 2 digital i/o pins (scl, sda, alm) vih input logic high 1.2 v vil input logic low 0.35 vol output logic low (sda, alm) iol = 4 ma 0.4 analog i/o pins (batd, cd) vith batd input threshold voltage 1.46 1.61 1.76 v vihyst batd input voltage hysteresis 0.1 ru batd internal pull-up resistor 1 m vcdoh cd output logic high ioh = 3 ma vcc - 0.4 v vinmin_cd minimum vin voltage for cd operation 0c to 50c 3.6 3.75 3.9 table 4. electrical characteristics (2.7 v < v cc < 4.5 v, -20 c to 70 c) (continued) symbol parameter conditions min typ max units
docid025792 rev 2 9/34 STC3117 electrical characteristics 34 figure 3. i 2 c timing diagram table 5. i 2 c timing - v io = 2.8 v, t amb = -20 c to 70 c (unless otherwise specified) symbol parameter min typ max unit f scl scl clock frequency 0 ? 400 khz t hd,sta hold time (repeated) start condition 0.6 s t low low period of the scl clock 1.3 t high high period of the scl clock 0.6 t su,dat setup time for repeated start condition 0.6 t hd,dat data hold time 0 0.9 t su,dat data setup time 100 ns t r rise time of both sda and scl signals 20+ 0.1c b 300 t f fall time of both sda and scl signals 20+ 0.1c b 300 t su,sto setup time for stop condition 0.6 s t buf bus free time between a stop and start condition 1.3 c b capacitive load for each bus line 400 pf 6'$ w i 6&/ w orz 9 lo w kgvwd w u w kggdw w vxgdw w kljk w vxvwd 9 lk *$3060'
application information STC3117 10/34 docid025792 rev 2 5 application information figure 4. example of an application schematic table 6. external component list name value tolerance comments rs 5 to 50 m 1 % to 5 % current sense resistor (2% or better recommended) c1 1 f supply decoupling capacitor c2 220 nf battery voltage input filter (optional) r1 1 k r2 battery detection function io voltage optional filter gnd battery pack other detection circuit rid c1 r1 STC3117 r2 scl sda alm cd vcc vin batd cs c2 rs
docid025792 rev 2 11/34 STC3117 functional description 34 6 functional description 6.1 battery monitoring functions 6.1.1 operating modes the monitoring functions incl ude the measurement of battery voltage, current, and temperature. a coulomb counter is available to track the soc when the battery is charging or discharging at a high rate. a sigma-delta a/d converter is used to measure the voltage, current, and temperature. the STC3117 can operate in two different mo des with different power consumption (see table 7 . mode selection is made by the vmode bit in register 0 (refer to table 12 for register 0 definition). in mixed mode, current is measured continuou sly (except for a conversion cycle every 4 s and every 16 s for measuring voltage and temp erature respectively). this provides the highest accuracy from the gas gauge. in voltage mode with no current sensing, a voltage conversion is made every 4 s and a temperature conversion every 16 s. this mode provides the lowest power consumption. it is possible to switch between the two operati ng modes to get the best accuracy during active periods, and to save power during st andby periods while still keeping track of the soc information. 6.1.2 battery voltage monitoring battery voltage is measured by using one c onversion cycle of the a/d converter every 4 s. the conversion cycle takes 2 13 = 8192 clock cycles. using the 32768 hz internal clock, the conversion cycle time is 250 ms. the voltage range is 0 to 4.5 v and resolution is 2.20 mv. accuracy of the voltage measurement is 0.5 % over the temperature r ange. this allows accu rate soc information from the battery open-circuit voltage. the result is stored in the reg_voltage register (see table 11 ). table 7. STC3117 operating modes vmode description 0 mixed mode, coulomb counter is active , voltage gas gauge runs in parallel 1 voltage gas gauge with power saving coulomb counter is not us ed. no current sensing.
functional description STC3117 12/34 docid025792 rev 2 6.1.3 internal temperature monitoring the chip temperature (close to the battery te mperature) is measured using one conversion cycle of the a/d converter every 16 s. the conversion cycle takes 2 13 = 8192 clock cycles. using the 32768 hz internal clock, the conversion cycle time is 250 ms. resolution is 1 c and range is -40 to +125 c. the result is stored in the reg_temperature register (see table 11 ). 6.1.4 current sensing in mixed mode current sensing is available on ly in mixed mode (vmode=0). the voltage drop across the sense resistor is integrated during a conversion period and is input to the 14-bit sigma-delta a/d converter. using the 32768 hz internal clock, the conversion cycle time is 500 ms for a 14-bit resolution. the lsb value is 5.88 v. the a/d converter output is in two ? s complement format. when a conversion cycle is completed, the result is added to the coulomb counter accumulator and the number of conversions is incremented in a 16-bit counter. the current register is updated after ea ch conversion (that is: once per 500-ms measurement cycle). the result is stor ed in the reg_current register (see table 11 ). average current register in mixed mode, an average value of the current measurement is calculated after each current measurement with a time constant of 2 s. the register reg_avg_curren t (2 bytes) holds the average current when vmode=0. the lsb of reg_avg_current is 1/4 the lsb of reg_current, that is 1.47 v. 6.1.5 soc change rate in voltage mode current sensing is not available in voltage mo de (vmode=1). instead, an estimation of the soc change rate is provided in the reg_avg_current register. the soc change rate is updated after each soc calculation (that is: once per 4-s measurement cycle) and is averaged with a time constant of 64 seconds. it is possible to write an initial estimation into the reg_avg_current register to speed-up the soc change rate settling time. the reg_avg_current register (2 bytes) holds the soc change rate when vmode=1. the lsb of reg_avg_current is 0.008789 c (by definition, 1 c means 100% soc change in 1 h).
docid025792 rev 2 13/34 STC3117 functional description 34 6.2 STC3117 gas gauge architecture 6.2.1 coulomb counter the coulomb counter is used to track the soc of the battery when the battery is charging or discharging at a high rate. each current co nversion result is accumulated (coulomb counting) for the calculation of the relative soc value based on the configuration register. the system controller can control the coulomb counter and set and read the soc register through the i 2 c control registers. figure 5. coulomb counter block diagram the reg_cc_cnf value depends on battery capa city and the current sense resistor. it scales the charge integrated by the sigma delta converter into a percentage value of the battery capacity. the default value is 395 (corresponding to a 10-m sense resistor and 1957-mah battery capacity). the coulomb counter is inactive if the vmode bi t is set, this is the default state at power- on-reset (por) or reset (vmode bit = 1). writing a value to the register reg_soc (mixed mode soc) forces the coulomb counter gas gauge algorithm to restart from this new soc value. reg_cc_cnf register is a 16-bit integer valu e cc_cnf that is calculated as shown in equation 1 : equation 1 rsense is in m and cnom is in mah. example: rsense =10 m , cnom = 1500 mah, cc_cnf = 303 reg_current register register reg_counter 16-bit counter reg_cc_cnf register ad converter eoc cs gnd current filter to s o c management coulomb counter calculator reg_avg_current register cc_cnf rsense cnom 49.556 ? =
functional description STC3117 14/34 docid025792 rev 2 6.2.2 voltage gas gauge algorithm no current sensing is needed for the voltage gas gauge. an internal algorithm precisely simulates the dynamic behavior of the battery and provides an estimation of the ocv. the battery soc is related to the ocv by means of a high-precision reference ocv curve built into the STC3117. any change in battery voltage causes the algorithm to track both the ocv and soc values, taking into account the non-linear characteristi cs and time constants related to the chemical nature of the li-ion and li-po batteries. a single parameter fits the algorithm to a specific battery. the default value provides good results for most battery chemistries used in hand-held applications. figure 6. voltage gas gauge block diagram voltage gas gauge algorithm registers the reg_vm_cnf configuration register is used to configure the parameter used by the algorithm based on battery characteristic. th e default value is 321 (corresponding to 160 m internal battery impedance and 1957 mah cnom battery capacity). the reg_ocv register holds the estimated ocv value corresponding to the present battery state. the reg_ocvtab and reg_soctab registers define the ocv curve for a given battery type; the default power-up values can be updated at software initialization. the reg_vm_cnf register is a 12-bit integer value and is calculated from the averaged internal resistance and nominal capacity of the battery as shown in equation 2 : equation 2 ri is in m and cnom is in mah. example: ri = 250 m , cnom =1500 mah, vm_cnf= 384 voltage mode algorithm to s o c management (vm) reference ocv curve ad converter vin register reg_voltage register reg_vm_cnf register reg_ocv register reg_ocvtab register reg_soctab vm_cnf ri cnom 977.78 ? =
docid025792 rev 2 15/34 STC3117 functional description 34 6.2.3 mixed mode gas gauge system the STC3117 implements a mixed mode gas gauge (optimgauge tm 1) that uses both the coulomb counter (cc) and the voltage mode (vm) algorithm to track the battery soc in all application conditions and automatically pr ovide the optimum soc information. the vm algorithm cancels any long-term errors and prevents the soc drift problem that is commonly found in cc-only solutions. the STC3117 automatically selects the best method based on the relaxation timer (see section 6.4: current monitoring ) as follows: when a low-power application state is detected by the relaxation timer, the soc reported by the STC3117 is the vm soc, otherwise the cc soc is reported. the STC3117 manages the transitions between the vm and cc modes without discontinuity by adjusting the vm and the cc soc to ensure smooth soc variations without jumps in any ap plication conditions. the current mixed mode state is indicated by the gg_vm bit in the reg_ctrl register: gg_vm=1 means the reported soc is the vm soc, otherwise the soc is the cc soc. note: when the application enters standby mode, the STC3117 can be put into power-saving mode by setting the vmode bit to 1 in the reg_mode register. only the vm gas gauge stays active, the cc is stopped, and the power consumption is reduced. figure 7. mixed mode gas gauge block diagram adjustment registers the registers reg_cc_adj and reg_vm_adj are signed 16-bit registers. they accumulate the adjustment quantities made to the soc values by the embedded mixed mode algorithm: ? reg_cc_adj = reg_soc ? (unadjusted cc soc) ? reg_vm_adj = reg_soc ? (unadjusted vm soc) these registers can be used by the system a pplication to implement more sophisticated algorithms for improved performance and accuracy. writing to the reg_soc or re g_ocv initializes the two vm and cc algorithms to the corresponding soc value and clears reg_vm_a dj and reg_cc_adj. it is possible to write to the reg_soc, reg_ocv, reg_vm _cnf and reg_cc_cnf registers when the STC3117 is running without disturbing soc management. note: when writing to the reg_soc or reg_ocv re gisters, the resulting soc value is rounded to the nearest 1/64 % value (the least three bits of reg_soc are zero). voltage mode (vm) reg_soc register alarm management parameter tracking coulomb counter reg_vm_adj register reg_cc_adj register (cc) soc management gas gauge
functional description STC3117 16/34 docid025792 rev 2 6.3 alarm output the alm pin provides an alarm signal in case of low battery or fault condition. the output is an open drain, and an external pull-up resistor is needed in the application. writing the io0data bit to 0 forces the alm output low; writing the io0data bit to 1 lets the alm output reflect the battery condition. reading the io0data bit gives the state of the alm pin. when the io0data bit is 1, the alm pin is driv en low if any of the fo llowing conditions are met: ? the battery soc estimation from the mi xed algorithm is less than the programmed threshold (if the alarm function is enabled by the alm_ena bit) ? the battery voltage is less than the programmed low voltage level (if the alm_ena bit is set) ? the batfail bit is set (if the alm_ena bit is set) low-voltage or low-soc alarms when a low-voltage or low-soc condition is triggered, the STC3117 drives the alm pin low and sets the alm_volt or alm_soc bit in reg_ctrl. the alm pin remains low (even if the conditions disappear) until the software writes the alm_volt and alm_soc bits to 0 to clear the interrupt. clearing the alm_volt or al m_soc while the co rresponding low-vo ltage or low-soc condition is still true does not g enerate another interr upt; this condition must disappear first and must be detected again before another interrupt (alm pin driven low) is generated for this alarm. the other alarm condition, if not yet triggered, can still generate an interrupt. usually, the low-soc alarm occurs first to warn the application of a low battery condition, then if no action is taken and the battery discharges further, the low-voltage alarm signals a nearly-empty battery condition. at power-up, or when the STC3117 is reset, the soc and voltage alarms are enabled (alm_ena bit = 1). the alm pin is in high-imp edance directly after a por and is driven low if the soc and/or the voltage is below the de fault thresholds (1% soc, 3.00 v), after the first ocv measurement and soc estimation. the reg_soc_alm register holds the relative so c alarm level in 0.5 % units (0 to 100 %). default value is 2 (i.e. 1 % soc). the reg_alarm_voltage holds the low voltage threshold and can be programmed over the full scale voltage range with 17.60 (2.20*8) mv steps. default value is 170 (i.e. 3.00 v). batfail alarm the batfail bit in reg_ctrl reflects the battery swap event: batfail bit is set when the batd signal rises above the batd threshold (1.61 v typ) for more than 0.5 s. and is reset by writing 0 to the batfail bit if the batd si gnal is below the batd threshold (if batd is still above 1.61 v, then batf ail bit can not be cleared). the STC3117 drives the alm pin low when the batfail bit is set and releases the alm pin when the batfail bit is cleared.
docid025792 rev 2 17/34 STC3117 functional description 34 6.4 current monitoring the battery average current is monitored and is used in conjunction with a timer to implement a battery relaxation timer. battery relaxation timer the battery relaxation timer is used to detect a light-load, low-power condition. the reg_cmonit_count register is an 8-bit, read-only counter that is incremented every 4 s when the average current is inside a window defined by positive and negative thresholds set by the reg_current_thres register, and decremented every 500 ms when the current is outside the thresholds. when the counter reaches its maximum value set by the reg_cmonit_max register, a low-power condition is reported to the mixed mode algorithm causing vm mode to be used. when the counter reaches its minimum value (0), a high-power condition is reported and cc mode is used. the reg_cmonit_max register sets the maximu m value of the counte r. with the default value (120 dec), the counter provides an 8-minute delay when switching from cc to vm mode and a 1-minute delay when switching from vm to cc mode. the reg_current_thres register is an 8- bit r/w register set by the gas gauge firmware from the i 2 c. it holds the threshold amplitude in bits 0 to 6 (unsigned value applicable for both positive and negative thresholds). bit 7 of reg_current_thres is reserved and must be set to zero for operation of the current monitoring counter as a relaxation timer. the lsb value of the re g_current_thres is 47.04 v and provides a range of 0 to 6 mv. it is possible to set the counter to zero or the maximum value using the force_cc and force_vm bits in the reg_mode regi ster. these bits are self-clearing.
functional description STC3117 18/34 docid025792 rev 2 6.5 power-up and ba ttery swap detection when the STC3117 is powered up at first battery insertion (power-on reset) or after a soft reset condition (pordet bit set by host), an automatic battery voltage, current and temperature measurement cycle is made immediately after startup and debounce delay. this feature enables the system controller to get the soc of a newly inserted battery based on the ocv. the cd pin controls the battery charger to inhibit the charge during the initial ocv measurement. the cd output is validated duri ng the power-up/restart sequence but is actually driven high only if the battery is pr esent (batd < 1.61v) and the battery voltage is higher than a threshold (vin > vinmin_cd) at the beginning of the restart sequence. the cd pin can be driven high under software control by using the bit force_cd in the reg_mode register. the batd pin senses the presence of the battery independently of the battery voltage. figure 8. batd and cd internal architecture overview the batd pin is an analog i/o. the input detection threshold is typically 1.61 v. the cd pin is an output connected to the v cc level when active. otherwise, it is high impedance. the batd pin can be connected to the ntc sensor or to the identification resistor of the battery pack. by default, the STC3117 provides an internal pull-up resistor for the detection of battery removal. the internal resistor can be disabled by clearing the bit batd_pu in the reg_mode register. when disabled, an external pull-up resistor or another device has to pull the batd pin high. cd batd v cc cd_drive 1.61 v + - vinmin_cd level vin + - &
docid025792 rev 2 19/34 STC3117 functional description 34 figure 9. timing diagram details of the power-up and restart sequence battery swap detection a battery swap can be detected in two ways: ? the battery voltage drops below the undervoltage lockout (uvlo) for more than tdel ? the batd signal rises above the batd threshold (1.61 v typ) for more than tdel the tdel delay is 0.5 s. using the 0.5 s filter provides robust battery swap detection and prevents false battery swap detection if short contact bouncing occurs at the battery terminals due to mechanical vibrations or shocks. this also prevents false detections in case of short battery voltage drops and protects the application against high surge currents at low temperatures. following a battery swap detection and after the battery voltage goes back above uvlo and the batd level returns to low level, the STC3117 is on hold with new voltage and current measurements in the corresponding registers. the system has to restart the STC3117 by doing a device soft reset i.e. by setting the pordet bit to 1 in the reg_ctrl register and restoring the parameters (if ne eded). to recover the event, either use the measured voltage and current to define a new ocv voltage, or restore a previous soc state. the occurrence of the battery swap event is indicated by the batfail and uvlod bits in the reg_ctrl register. vcc uvlo internal 1ma sink current voltage measurement delay cd pin (low means hiz) ocv meas. application can start, charge is enabled current measurement te m p era t ure measurement 125 ms conversion counter x 0 1 23 vinmin_cd ibat meas. (arbitrary vcc waveforms only to illustrate the function) ?dead? battery ?good? battery gams1601141520cb ?good? battery ?dead? battery 375 ms 125 ms 125 ms 250 ms 100 ms
functional description STC3117 20/34 docid025792 rev 2 figure 10. restart in case of battery swap vcc uvlo batd short uvlo event < 0.5s no restart, no operation interruption batfail=0 uvlod=0 <0.5s short battery disconnection event < 0.5s no restart, no operation interruption batfail=0 uvlod=0 <0.5s por battery removal, fast vcc drop, restart at powerup pordet=1 batfail=0 uvlod=0 1.61v
docid025792 rev 2 21/34 STC3117 i 2 c interface 34 7 i 2 c interface 7.1 read and write operations the i 2 c interface is used to control and read the current accumulator and registers. it is compatible wit h the philips i 2 c bus? (version 2.1). it is a slave serial interface with a serial data line (sda) and a serial clock line (scl). ? scl: input clock used to shift data ? sda: input/output bidirectional data transfers a filter rejects the potential spikes on the bus data line to preserve data integrity. the bidirectional data line supports transfers up to 400 kbit/s (fast mode). the data are shifted to and from the chip on the sda line, msb first. the first bit must be high (start) followed by the 7-bit device address and the read/write control bit. the default device address value is 1110 000. the STC3117 then sends an acknowledge at the end of an 8-bit long sequence. the next eight bits correspond to the register address followed by another acknowledge. the data field is the last 8-bit long sequence sent, followed by a final acknowledge. figure 11. read operation table 8. device address format bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1110000r/w table 9. register address format bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 regaddr7 regaddr6 regaddr5 regaddr4 regaddr3 regaddr2 regaddr1 regaddr0 table 10. register data format bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data7 data6 data5 data4 data3 data2 data1 data0 6wduw 'hylfhdggu 5hjdgguhvv elwv $ 5hvwduw 'hylfhdggu $ 5hjgdwd elwv $ 5hjgdwd elwv $ 5hjgdwd elwv $ $gguhvv q 6wduwelw 6'$idoolqjzkhq6&/ elwv elwv 6wrs $ : 6wrselw 6'$ulvlqjzkhq6&/ 5hvwduwelw vwduwdiwhudvwduw 0dvwhu 6odyh $fnqrzohgjh 6'$irufhgorzgxulqjd6&/forfn 5 $gguhvv q *$3060'
i 2 c interface STC3117 22/34 docid025792 rev 2 figure 12. write operation 6wduw 'hylfhdggu 5hjdgguhvv elwv $ 5hjgdwd $ 5hjgdwd elwv $ 5hjgdwd elwv $ $gguhvv q 6wduwelw 6'$idoolqjzkhq6&/ elwv elwv 6wrs $ : 6wrselw 6'$ulvlqjzkhq6&/ 5hvwduwelw vwduwdiwhudvwduw $gguhvv q *$3060'
docid025792 rev 2 23/34 STC3117 i 2 c interface 34 7.2 register map and description 7.2.1 register map the register space provides 31 control regi sters, 16 read/write ram working registers reserved for the gas gauge algorithm, and 48 ocv table registers. mapping of all registers is shown in table 11 . detailed descriptions of register s 0 (reg_mode) and 1 (reg_ctrl) are shown in table 12 and table 13 . all registers are reset to default values at power-on or reset, and the pordet bit in register reg_ctrl is used to indicate the occurrence of a power-on reset. table 14 gives a detailed description of the internal ocv table registers. table 11. register map name address (decimal) type por soft por description lsb control registers 0 to 30 reg_mode 0 r/w mode register reg_ctrl 1 r/w control and status register reg_soc (l-h) 2-3 r/w battery soc (2 bytes) 1/512 % reg_counter (l-h) 4-5 r 0x00 0x00 number of conversions (2 bytes) reg_current (l-h) 6-7 r 0x00 0x00 battery current (2 bytes) 5.88 v reg_voltage (l-h) 8-9 r 0x00 0x00 bat tery voltage (2 bytes) 2.2 mv reg_temperature 10 r 0x00 0x00 temperature 1 c reg_avg_current (l-h) 11-12 r/w 0x00 0x00 battery average current or soc change rate (2 bytes) 1.47 v or 0.008789 c reg_ocv (l-h) 13-14 r/w 0x00 0x00 ocv register (2 bytes) 0.55 mv reg_cc_cnf (l-h) 15-16 r/w 395 395 coulomb counter gas gauge configuration (2 bytes) reg_vm_cnf (l-h) 17-18 r/w 321 321 voltage gas gauge algorithm parameter(2 bytes) reg_alarm_soc 19 r/w 0x02 0x02 soc alarm level (default = 1 %) 1/2 % reg_alarm_voltage 20 r/w 0xaa 0xaa battery low voltage alarm level (default is 3 v) 17.6 mv reg_current_thres 21 r/w 0x0a 0x0a current threshold for current monitoring (bits 6-0) 47.04 v reg_cmonit_count 22 r 0x78 0x78 current monitoring counter reg_cmonit_max 23 r/w 0x78 0x78 maximum counter value for current monitoring reg_id 24 r 0x16 0x16 part type id = 16h reg_cc_adj (l-h) 27-28 r 0x00 0x00 coulomb counter adjustment register (2 bytes) 1/512 % reg_vm_adj (l-h) 29-30 r 0x00 0x00 voltage mode adjustment register (2 bytes)
i 2 c interface STC3117 24/34 docid025792 rev 2 7.2.2 register description values held in consecutive registers (such as the soc value in the reg_soc register pair) are stored with low bits in the low-address register (l) and high bits in the high-address register (h). the registers must be read with a single i 2 c access to ensure data integrity. it is possible to read multip le values in one i 2 c access. all values must be consistent. the soc data are coded in binary format and the lsb of the low byte is 1/512 %. the battery current is coded in 2?s comple ment format and the lsb value is 5.88 v. the battery voltage is coded in 2?s complement format and the lsb value is 2.20 mv. the temperature is coded in 2?s complement format and the lsb value is 1c. ram registers 32 to 47 reg_ram0 32 r/w 0x00 0x00 working register 0 for gas gauge ... ... ... reg_ram15 47 r/w 0x00 0x00 working register 15 for gas gauge ocv table registers 48 to 95 reg_ocvtab0 (l-h) to reg_ocvtab15 (l-h) 48-49 to 78-79 r/w see table 14 see table 14 ocv points, 2 bytes per point (32 registers) 0.55 mv reg_soctab0 to reg_soctab15 80 to 95 r/w see table 14 see table 14 soc points, 1 byte per point (16 registers) 1/2 % table 11. register map (continued) name address (decimal) type por soft por description lsb
docid025792 rev 2 25/34 STC3117 i 2 c interface 34 7.2.3 reg_mode and reg_ct rl register description table 12. reg_mode - address 0 name position type def. description vmode 0 r/w 1 0: mixed mode (coulomb counter active) 1: power saving voltage mode batd_pu 1 r/w 1 batd internal pull-up enable 0: internal pull-up disconnected 1: internal pull-up connected force_cd 2 r/w 0 0: cd driven by internal logic (refer to section 6.5 ) 1: cd output is forced high alm_ena 3 r/w 1 alarm function 0: disabled 1: enabled gg_run 4 r/w 0 0: standby mode. accumulator and counter registers are frozen, gas gauge and battery monitor functions are in standby. 1: operating mode force_cc 5 r/w 0 forces the relaxation ti mer to switch to the coulomb counter (cc) state. write 1, self clear to 0 relaxation counter = 0 force_vm 6 r/w 0 forces the relaxation time r to switch to voltage mode (vm) state. write 1, self clear to 0 relaxation counter = relax_max 7 unused
i 2 c interface STC3117 26/34 docid025792 rev 2 table 13. reg_ctrl - address 1 name position type def. description io0data 0 rx alm pin status 0 = alm input is low 1 = alm input is high w1 alm pin output drive 0 = alm is forced low 1 = alm is driven by the alarm conditions gg_rst 1 w 0 0: no effect 1: resets the conversion counter gg_rst is a self-clearing bit. gg_vm 2 r 0 voltage mode active 0 = reg_soc from coulomb counter mode 1 = reg_soc from voltage mode batfail 3 r/w 0 battery remova l (batd high). write 0 to clear (effective only if batd low) (write 1 is ignored) pordet 4 r1 power on reset (por) detection bit 0 = no por event occurred 1 = por event occurred w0 soft reset 0 = release the soft-reset and clear the por detection bit, 1 = assert the soft-reset and set the por detection bit. this bit is self clearing. alm_soc 5 r/w 0 set with a low-soc condition. cleared by writing 0. alm_volt 6 r/w 0 set with a low-voltage condition. cleared by writing 0. uvlod 7 r/w 0 uvlo event detection. cleared by writing 0.
docid025792 rev 2 27/34 STC3117 i 2 c interface 34 7.2.4 ocv table register description table 14. default ocv tabl e and ocv table registers table entry default soc default ocv soc register ocv register % hex code mv hex code 0 0 00 3300 1770 reg_soctab0 reg_ocvtab0 1 3 06 3541 1926 reg_soctab1 reg_ocvtab1 2 6 0c 3618 19b2 reg_soctab2 reg_ocvtab2 3 10 14 3658 19fb reg_soctab3 reg_ocvtab3 4 15 1e 3695 1a3e reg_soctab4 reg_ocvtab4 5 20 28 3721 1a6d reg_soctab5 reg_ocvtab5 6 25 32 3747 1a9d reg_soctab6 reg_ocvtab6 7 30 3c 3761 1ab6 reg_soctab7 reg_ocvtab7 8 40 50 3778 1ad5 reg_soctab8 reg_ocvtab8 9 50 64 3802 1b01 reg_soctab9 reg_ocvtab9 10 60 78 3863 1b70 reg_soctab10 reg_ocvtab10 11 65 82 3899 1bb1 reg_soctab11 reg_ocvtab11 12 70 8c 3929 1be8 reg_soctab12 reg_ocvtab12 13 80 a0 3991 1c58 reg_soctab13 reg_ocvtab13 14 90 b4 4076 1cf3 reg_soctab14 reg_ocvtab14 15 100 c8 4176 1da9 reg_soctab15 reg_ocvtab15
package information STC3117 28/34 docid025792 rev 2 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
docid025792 rev 2 29/34 STC3117 package information 34 8.1 flip chip csp 1.49 x 1.594 x 0.4 mm (n5) with coating ball printing package information figure 13. flip chip csp 1.49 x 1.594 x 0.4 mm (n5) package mechanical drawing 1. the terminal a1 on the bump side is i dentified by a distinguishing feature - for instance, by a circular ?clear area? typically 0.1 mm in di ameter and/or a missing bump. 2. the terminal a1, on the back side, is identified by a distinguishing feature - for instance, by a circular ?clear area? typically 0.2 mm in diameter depending on the die size. d1 fd e c b a se fe1 fe2 e e1 3 2 1 bottom view top view e d ccc c a a1 a2 c ?b $ gams1701141057cb a1 (see note 1 and 2)
package information STC3117 30/34 docid025792 rev 2 table 15. flip chip csp 1.49 x 1.594 x 0.4 mm (n5) package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.545 0.60 0.655 0.021 0.024 0.026 a1 0.17 0.20 0.23 0.007 0.008 0.009 a2 0.38 0.4 0.42 0.015 0.016 0.017 b 0.23 0.26 0.29 0.009 0.010 0.011 d 1.43 1.46 1.49 0.056 0.057 0.059 d1 0.8 0.031 e 1.534 1.564 1.594 0.060 0.062 0.063 e1 0.8 0.031 e0.4 0.016 se 0.015 0.001 fd 0.32 0.33 0.34 0.013 0.013 0.013 fe1 0.357 0.367 0.377 0.014 0.014 0.015 fe2 0.387 0.397 0.407 0.015 0.016 0.016 $ 0.05 0.002 ccc 0.05 0.002
docid025792 rev 2 31/34 STC3117 package information 34 figure 14. flip chip csp 1.49 x 1.594 x 0.4 mm (n5) package footprint recommendation (top view) c b a 3 2 1 0.80 grid placement area 0.80 0.40 0.40 ?0.22 gams1701141127cb
package information STC3117 32/34 docid025792 rev 2 figure 15. flip chip csp 1.49 x 1.594 x0.4 mm (n5) package reflow profile recommendation gams1701141140cb
docid025792 rev 2 33/34 STC3117 ordering information 34 9 ordering information 10 revision history table 16. order code order code temperature range package packing marking STC3117ijt -40c to +85c csp 9-bump tape and reel vwv table 17. document revision history date revision changes 23-jul-2014 1 initial release 19-jan-2015 2 updated ?low power? value in features updated section 6.1.4: current sensing in mixed mode added section 6.1.5: soc change rate in voltage mode updated figure 5: coulomb counter block diagram updated example of equation 2 re-wrote section 6.2.3: mixe d mode gas gauge system re-wrote section 6.4: current monitoring updated section 6.5: power-up and battery swap detection . updated table 11: register map updated table 12: reg_mode - address 0 updated table 13: reg_ctrl - address 1
STC3117 34/34 docid025792 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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